Welltech SPCI2S Intel NetStructure SS7 Boards Uživatelský manuál stáhnout pdf (Strana 70)

SS7 Programmer’s Manual for SPCI2, SPCI4 and CPM8 Issue 2 Page 70

Parameter Description:

bus_speed

This parameter is used to set the CT bus speed, the permissible values are as

follows:

Value Bus speed

0 No change

2 4.096 MHz (Reserved for future use)

3 8.192 MHz

clk_mode

This parameter determines the clocking mode for the board, the permissible

values are as follows:

Value Clock Mode

0 No change

1 CT bus Primary Master, driving Clock Set A

2 CT bus Secondary Master, driving Clock Set B

3 CT bus Slave, initially using Clock Set A

4 CT bus disabled

10 CT bus Primary Master, driving Clock Set B

11 CT bus Secondary Master, driving Clock Set A

12 CT bus Slave, initially using Clock Set B

When mode 4 is selected (“CT bus disabled”) the card is electrically isolated

from the other cards using the CT bus. The CT bus connection commands may

still be used, but the connections made will only be visible to this card. When

using this mode, the on-board clocks will be synchronised to the configured

pll_clk_src reference.

If the card is configured to be Slave to the CT bus then it will automatically

switch between using Clock Set A and Clock Set B if it detects a failure on the

current clock set.

When a card is acting as Primary Master it uses the clock reference set by the

pll_clk_src parameter to drive the CT bus clock.

As Secondary Master the pll_clk_src should be set to an appropriate source

ready for use if the card acting as Primary Master stops driving the CT bus

clock. Until this time, the on-board clocks on the Secondary Master card will be

synchronised to the CT bus clock provided by the Primary Master.

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Welltech SPCI2S Intel NetStructure SS7 Boards Uživatelský manuál Strana 70